Low power applications, as well as certain high performance applications, typically require a slowing down of the system clock by dividing the system clock and switching the circuit to a low frequency clock, and then back to a higher frequency, as required by the application.
Such clock switching circuits are also used in built in self test (BIST) circuits for dynamic fault detection. These BIST circuits determine the optimum clock frequency at which the associated circuit under test can be run error-free.
This switching of clock lines from one frequency to another is called clock scaling and is typically done “on the fly” without turning off the circuit. However, this switching may cause glitches on clock lines resulting in malfunctioning of the circuit.
Techniques for clamping and introducing multi-cycle dead time between clock switching have been proposed, see, e.g., U.S. Pat. Nos. 4,853,653, 4,965,524, 4,970,405, 5,315,181, 5,537,062, 5,652,536, 5,808,485 and 5,623,223. However, introducing multi-cycle dead time is inappropriate for certain applications, such as built in self test circuits. The amount of dead time in these circuits is dependent on the number of clocks to be switched and the period of the lowest frequency clock.